Code:
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* nVidia nForce2 Data Base *
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1) AGP Controller Latency
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PCI Bus#0 Dev#30 Func#0 Offset#0D
0D
- 16 clock : 10
- 32 clock : 20
- 64 clock : 40
- 96 clock : 60
- 128 clock : 80
- 160 clock : A0
- 192 clock : C0
- 224 clock : E0
- 255 clock : FF
2) AGP Bus Latency
******************
PCI Bus#0 Dev#30 Func#0 Offset#1B
1B
- 16 clock : 10
- 32 clock : 20
- 64 clock : 40
- 96 clock : 60
- 128 clock : 80
- 160 clock : A0
- 192 clock : C0
- 224 clock : E0
- 255 clock : FF
3) PCI Latency
*************
PCI Bus#0 Dev#8 Func#0 Offset#1B
1B
- 16 clock : 10
- 32 clock : 20
- 64 clock : 40
- 96 clock : 60
- 128 clock : 80
- 160 clock : A0
- 192 clock : C0
- 224 clock : E0
- 255 clock : FF
4) CPU Disconnect Function
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PCI Bus#0 Dev#0 Func#0 Offset#6C,6D,6E,6F
6C 6D 6E 6F
- Enable : 01 FF 01 1F/9F
- Disable : 01 FF 01 8F
5) Command Per Clock (T1/T2)
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PCI Bus#0 Dev#0 Func#1 Offset#84,85,86,87
84 85 86 87
- Enable : F3 13 0F 03
- Disable : F3 13 0F 23
WARNING! (Not Editable after boot, Can only be set before memory sizing)
6) Alpha Memory Setting
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PCI Bus#0 Dev#0 Func#1 Offset#94,95,96,97
94 95 96 97
- T(DOE) : x Selectable Value: 0,1,2,3,4,5,6
- T(RRD) : x Selectable Value: 0,1,2,3,4,5,6
- T(W2P) : x Selectable Value: 0,1,2,3,4,5,6
- T(W2R) : x Selectable Value: 0,1,2,3,4,5,6
- T(REXT) : x Selectable Value: 0,1,2,3
- T(R2P) : x Selectable Value: 0,1,2,3,4,5,6
- T(R2W) : x Selectable Value: 0,1,2,3,4,5,6
- reserved: - Selectable Value: -
- Offset 94 = XY
X= T(R2W) Selectable Value: 0,1,2,3,4,5,6
Y= Reserved -
- Offset 95 = XY
X= T(REXT) Selectable Value: 0,1,2,3,
Y= T(R2P) Selectable Value: 0,1,2,3,4,5,6
- Offset 96 = XY
X= T(W2P) Selectable Value: 0,1,2,3,4,5,6
Y= T(W2R) Selectable Value: 0,1,2,3,4,5,6
- Offset 97 = XY
X= T(DOE) Selectable Value: 0,1,2,3,4,5,6
Y= T(RRD) Selectable Value: 0,1,2,3,4,5,6
7) Normal Memory Setting
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PCI Bus# Dev# Func# Offset#
- T(RAS) :
- T(RCD-Read) :
- T(RCD-Write) :
- T(RP) :
- CAS Latency :
- T(RC) :
- T(RFC) :
8) Side Band Addressing
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PCI Bus#0 Dev#0 Func#0 Offset#49
49
- Enable : 03
- Disable : 01
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