DRAM Configuration Low RegisterFunction 2: Offset 90h
How can there be 7 drive strengths for DFI when AMD64 memory controller D_DRV is one bit only ?D_DRV (D_DRV)—Bit 1. Controls the drive strength of the DRAM device outputs when the DRAM
is driving on a READ command. This bit is required by the DRAM in the Extended Memory
Register Set (EMRS) command. It applies to all outputs.
0 = Normal Drive (default)
1 = Weak Drive (beware)
I mean, why DFI has so many levels for drive strength ?
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