AMD memory controller vs HyperTransport

[TSFroggy]

After doing some research, I think that I have had these two things confused for a while. Is AMD's on-die memory controller linked to the memory by a HyperTransport link, or is HT only used to link the CPU and the chipset?

One other question. On AMD's website, it shows all A64 processors as having one "non coherent" HT link, with Opteron processors having up to 3 of both kinds of links (coherent and non coherent.) What is the difference between these?

[perkam]

After doing some research, I think that I have had these two things confused for a while.

Its 1:22 AM here, and I'm half asleep so my advise: do some more research lol.

Perkam

[ozzimark]

2:20

i'll try to help though.

first off, this picture of the K8 is layed out will help.
http://images.anandtech.com/reviews/...hammercore.gif
basically, the ht links and memory controller are seperate. and have nothing to do with eachother.
there is a crossbar between the core, memory controller and ht link(s), allowing for the connection of any two thereof.
for normal desktop a64's with one ht link this means you can connect:
core <--> memory controller
core <--> ht link
memory controller <--> ht link


though, i don't know the difference between a coherent and non-coherant ht link is. my best guess would be that the non-cohereant ht links can only connect to the chipset, while the coherant ones can also connect to other coherent links on other cpu's. though that doesn't really make sense.
so the only other option is that the non-coherent link babbles nonsense while the coherent one is somewhat intelligent?

[hchu]

perhaps a coherent link maintains cache coherency between processors?

[koei]

Since the north bridge use to be the memory controller on older general CPU and as well as current day Intels, the link between CPU and the bridge is I suppose called the coherent link? Having the mem controller seperately created latency and wiring issues as the addressing needed grew. So AMD decided to go with the integration route. HyperTransport is just a term AMD branded for the link they have with the CPU and on-die mem controller. Doesn't really mean much other than a cool name to get people's attention.

[EMC2]

--- TSFroggy ---

The mem controller and HT links are seperate entities, not sequential. For a little help read this thread. We were discussing dual-cores, but the info on the controller and HT links are still relevant and might help you out

Regarding the coherency question - it deals with whether or not the links are snooped (which is used to maintain coherency between the memory and cache... i.e. insure they contain the same data for the same address).

Peace

[ozzimark]

So AMD decided to go with the integration route. HyperTransport is just a term AMD branded for the link they have with the CPU and on-die mem controller.

if i'm not mistaken, you are saying that a hypertransport link connects the core and the memory controller?

[mad mikee]

If not:

to the world of xtreme.

Now get , we can use all the help we can get (D2oL)