What CAS, tRP, and all those others mean

To make our overclocks more successful, we should know what we are changing. Here is a description of some of the things we can change in A64 tweaker.

CAS Latency
The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs.

tWR - Write Recovery Time:
tWR is the number of clock cycles taken between writing data and issuing the precharge command. tWR is necessary to guarantee that all data in the write buffer can be safely written to the memory core.

tRAS - Row Active Time:
tRAS is the number of clock cycles taken between a bank active command and issuing the precharge command.

tRC - Row Cycle Time:
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
tRC = tRAS + tRP

tRCD - Row Address to Column Address Delay:
tRCD is the number of clock cycles taken between the issuing of the active command and the read/write command. In this time the internal row signal settles enough for the charge sensor to amplify it.

tRP - Row Precharge Time:
tRP is the number of clock cycles taken between the issuing of the precharge command and the active command. In this time the sense amps charge and the bank is activated.

tRRD - Row Active to Row Active Delay:
The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD.

tCCD - Column Address to Column Address Delay

tRD - Active to Read Delay ?:

tWTR - Internal Write to Read Command Delay:
tWTR is the delay that has to be inserted after sending the last data from a write operation to the memory and issuing a read command.

tRDA - Read Delay Adjust
(got it from here http://www.techpowerup.com/articles/overclocking/64)

update (little more info)

Max Asynce lantency= 00.0-15.0 in 1.0 incements.
I would suggest trying 5.0-10.0 depending on your ram. 5ns will problobly not allow much overclocking, and 7-8ns is usually the optimal

Read Preamble time= 02.0-09.5 nano sec, in 0.5 increments.

I would suggest 4.0-7.0 depending on ram. 4ns will probobly not allow for much overclocking, and 5-6ns is usually the optimal

Very nice! good guide there

jjcom

Hey, add read preamble and max async latency, cause thats the only thing I don't know. And maybe for the guide, add some common values such as what tccd uses, what bh5 uses, what is considered 'standard tight' and whats 'ultra tight' etc. Might make a sticky even.

If anything it'll be submitted on the front page's guide section...:D

jjcom

Which timing is most important for A64 performance?

For me CAS seems to make the largest difference by far; tRCD and tRP seem to make a noticable difference too.

Trcd seems to make the most difference over a large number of platforms.. cas2.5 and trcd2 is MUCH faster than cas2 and trcd3..

here are good settings for BH-5 (windbond, so maybe you might have to tweak for different BH-5)
Dram Frequency Set(Mhz)= 200(Mhz)(1/01)

Command Per Clock(CPC)= Enable(1T),

Cas Latency Control(tCL)= 2

RAS# to CAS# delay(tRCD)= 2

Min RAS# active timing(tRAS)=10

Row Precharge timing(tRP)= 2

Row Cycle Time(tRC)= 9

Row Refresh cyc time(tRFC)= 12

Row to Row Delay(also called Ras to Ras delay)(tRRD)=00, 02 also worked good

Write Recovery Time(tWR)= 2

Write to read Delay(tWTR)= 1

Read to Write delay(tRTW)=1

Refresh Period(tREF)=3120, and 3072 also worked good


Write CAS# Latency(tWCL)= 1
(got to 260 1:1 before it wouldn't go higher. This got me 33 sec PI)

I'll add it to the Xtreme Terminology thread.

Quote:

---

Originally Posted by Highland3r

Trcd seems to make the most difference over a large number of platforms.. cas2.5 and trcd2 is MUCH faster than cas2 and trcd3..

---

You're comparing the difference between CAS2.5 - 2 vs TRCD3 - 2. That's fundamentally wrong!

Yes, in that example, TRCD would make more of a difference, but it would be extremely minor (probably around 0.2%). On an XP, timings as a whole only make about a 3-4% difference.

CAS is the most important variable, though not by too much. Here's some data I pulled using 3DM01 back in the day: http://forums.extremeoverclocking.co...ings+bandwidth

:D Very good - PM to an ADMIN and make that a sticky..... :thumbsup:

:toast:

So when one sees "2-2-2-5", what does each of those refer to? I know the first is usually CAS latency, but beyond that?

i don't see a tRFC in there.

Quote:

---

Originally Posted by goto_dengo

So when one sees "2-2-2-5", what does each of those refer to? I know the first is usually CAS latency, but beyond that?

---

I believe the order is as follows...

1. Cas Latency
2. tRCD = RAS to CAS delay
3. tRP = RAS Precharge
4. tRAS = Active to Precharge

and if there is a 1T or 2T on the end its Command Rate :cool:

Wow that's very nice .... i know it'll make some new DFi users (like me ) happy :slobber:

I don't know if I am right.
From my experience:
CAS latancy depends on the speed of max async latency.
twtr, twr,trtw are the factors decide the performance of your bandwidth.
and the tref could be tricky. It depends on what type of bench(calculation) you do.
For like bandwidth, you wanna have 200, 3.9
when you do like super pi. you wanna have 100, 1.95

hope I am not wrong with that.:D
OPB

Really nice and forward explanations here...:thumbsup:
I can't help but think you need to have a good idea how memory works though to understand this. Anyone have a guide for that? :hehe:

Quote:

---

Originally Posted by moddolicous

here are good settings for BH-5 (windbond, so maybe you might have to tweak for different BH-5)
Dram Frequency Set(Mhz)= 200(Mhz)(1/01)

Command Per Clock(CPC)= Enable(1T),

Cas Latency Control(tCL)= 2

RAS# to CAS# delay(tRCD)= 2

Min RAS# active timing(tRAS)=10

Row Precharge timing(tRP)= 2

Row Cycle Time(tRC)= 9

Row Refresh cyc time(tRFC)= 12

Row to Row Delay(also called Ras to Ras delay)(tRRD)=00, 02 also worked good

Write Recovery Time(tWR)= 2

Write to read Delay(tWTR)= 1

Read to Write delay(tRTW)=1

Refresh Period(tREF)=3120, and 3072 also worked good


Write CAS# Latency(tWCL)= 1
(got to 260 1:1 before it wouldn't go higher. This got me 33 sec PI)

---

Mod, you have the same table for Corsair PC4400 Platinum cas 2,5????
I want tunning my memo but I cant......many options only for memos.... :mad:

Hello I search a diagram who illustrate correctly the DDR-Ram Timings Functionnement in order to better understand this principle... because most oc'ers use that commonly but nobody have a real description... :/

Can you help me to find this?

Im try to use EVEREST for tunning my memos for best result leaving from initial base.

Is there other selecter program to do that??

It would be great to see a table of the more obscure settings and what impact they have on performance or stability.

nice work modollicous. Bookmarked.

I agree with dexx, maybe some explanation or suggestions.

however, what about other memory tweaks info that are found on DFI's bios / A64Tweak? They are more advanced as far i'm concern.

Can anyone help me on how to use AMD64 memory tweakers
everytime i change the value my pc reboot or hang
pls guide step by step

There are certain timings you shouldn't change in A64 Tweaker, especially when already overclocked high. The ones that make my machine crash are Max Async Latency, tRP, CAS, and a maybe one or two more of the "major" ones. Others, such as Bank Cycle Time, etc, these are probably less "important" to most users, so they can usually be changed without problems.

just afew numbers & settings, but the combinations!
also every memory is kinda specific, even the same IC (but diff. week)
as an example could be my ballistix used - others can do with DDR1 ballistix more than 280+ MHz with 3-3-3-8 (or worse), while my stop at 283 (not a Hz more!)but can do 3-3-2-7 and other things tightened.
It's very difficult to describe everything, and how it works together!
It takes a lot of time to find the "sweet spot" or "peak".
Newbies just cant read one complete short article and understand everything, it isnt that easy. It's about learning it yourself, experiencing and testing it yourself! U cant have rules for everything because it depends on every components, BIOS, ... If it was so easy, I wouldnt bow to poeple like OPB and others